Welcome to TSMC's Second Quarter 2017 Earnings Conference and Conference Call. This is Elizabeth Sun, TSMC's Senior Director of Corporate Communications and your host for today. Today's event is webcast live through TSMC's website at www.tsmc.com. If you are joining us via the conference call your dialing lines are in listen only mode. As this conference is being viewed by investors around the world, we will conduct the event in English only. The format for today's event will be as follows: First, TSMC's Senior Vice President and CFO, Ms. Lora Ho, will summarize our operations in the second quarter of 2017, followed by our guidance for the third quarter of 2017, along with our key messages. Afterwards, TSMC's two Presidents and Co-CEOs, Dr. Mark Liu and Dr. C.C. Wei, will jointly provide our key messages, then we will open both the floor and the line for questions and answers. For those participants on the call, if you do not yet have a copy of the press release, you may download it from TSMC's website at www.tsmc.com. Please also download the summary slides in relation to today's earnings and conference presentations. As usual, I would like to remind everybody that today's discussions may contain forward-looking statements that are subject to significant risks and uncertainties, which could cause actual results to differ materially from those contained in the forward-looking statements. Please refer to the safe harbor notice that appears on our press release. And now I would like to turn the podium to TSMC's CFO, Ms. Lora Ho, for the summary of operations and current quarter guidance.

Thank you, Elizabeth. Good afternoon, everyone. Thank you for joining us today. My presentation will starting from the financial highlights for the second quarter, followed by the guidance for the third quarter. Second quarter revenue decreased 8.6% quarter-over-quarter and 3.6% year-over-year. This sequential decline reflecting supply chain inventory management, mobile product seasonality and appreciation in NT dollar against the U.S. dollar. In U.S. dollar terms, second quarter revenue was $7.06 billion, about 5.9% decrease Q-over-Q by 3.2% increase year-over-year. Gross margin was 50.8%, 1.1 percentage lower than the first quarter, mainly due to the unfavorable foreign exchange rate. Operating expenses ratio rose to 11.9% as our revenue decreased more than the expense decrease. Operating margin decreased 1.9 percentage points sequentially to reach 38.9% in the second quarter. As I said in my last quarterly conference, the second quarter corporate tax rate would be 23% due to the accrual of 10% undistributed retained earnings tax. The tax rate will fall back to 10% and 11% level in the second half, and the full year tax rate will remain at 13% to 14%. Overall, our second quarter EPS was $2.56 and ROE was 19%. Now let's take a look at wafer revenue contribution by application. During the second quarter, Communication, Computer and Consumer decreased 10%, 14% and 7%, respectively, while Industrial/Standard increased 9%. In terms of revenue by technology, 10-nanometer process technology contributed 1% of total wafer revenue during the second quarter, while the combined revenue from 16- and 20-nanometer accounted for 26% of wafer revenue in the second quarter, and 28-nanometer represented 27% of total wafer revenue. So advanced technology, defined as 28-nanometer and below accounted for 54% of our total wafer revenue in the second quarter. Moving on to the balance sheet. We ended the second quarter with cash and marketable securities of TWD 659 billion, essentially flat from the first quarter. On the liabilities side, current liabilities increased by TWD 202 billion as we accrued about TWD 182 billion for cash dividends, which will be paid out this month. On financial ratios, accounts receivable turnover days remained at 47 days, while days of inventory increased eight days to 52 days, primarily due to the higher work-in-process inventory for the 10-nanometer to support production ramp in third quarter. Now let me make a few comments on cash flow and CapEx. During the second quarter, we generated about TWD 103 billion cash from operations. We spent TWD 105 billion in capital expenditure, so the free cash flow was an outflow of about TWD 2 billion. We also disposed TWD 5 billion of fixed income investment. As a result, overall, our cash balance increased by about TWD 6 billion to TWD 570 billion at the end of the second quarter. In U.S. dollar terms, our first half capital expenditure was US$6.8 billion. Full year capital budget remained at about US$10 billion. Before I conclude the financial summary, I would like to point out the impact of foreign exchange rate on our revenue. As I mentioned to you last time, nearly all TSMC's revenue is in U.S. dollar. The sensitivity of our revenue to U.S. dollar versus NT dollar exchange rate is nearly 100%. And the sensitivity of both our gross margin and operating margin to 100 basis points exchange rate fluctuation is about 40 basis points. In the first quarter, NT dollars appreciated by 2% sequentially, followed by another 3% appreciation in the second quarter. Year-over-year, NT dollars appreciated 6% in first quarter and 6.6% in second quarter. Therefore, our first half 2017 revenue in NT dollars only went up by 5.3% compared to first half 2016, whereas in U.S. dollars, our revenue in the first half grew 12.2% from first half 2016. This is better than what we stated in the January investor conference that our first half 2017 revenue would grow by about 10% from first half 2016 in U.S. dollar terms. Now let me turn into third quarter guidance. First of all, starting from this quarter, our quarterly revenue guidance will be given in U.S. dollar only. We make these changes because nearly of our revenue -- all our revenue are in U.S. dollars and that giving revenue guidance in U.S. dollar more truthfully reflects our business expectation. So based on current business outlook, we expect third quarter revenue to be between USD 8.12 billion and USD 8.22 billion. Based on assumptions of TWD 30.30 to USD 1, our third quarter gross margin is expected to be between 48.5% and 50.5%. Our third quarter operating margin is expected to be between 37% and 39%. Since we begin a significant ramp of our 10-nanometer production in third quarter, we expect the 10-nanometer ramp will impact our second half 2017 gross margin by about 2 to 3 percentage points. The impact on third quarter margins has already been reflected in our third quarter guidance, which I just provided. Thank you. Now I'd like to turn the microphone to Mark for his comments.

Good afternoon, ladies and gentlemen. Let me continue to deliver my key messages. First, I want to talk about our near-term demand. Because again, all our customer orders are in U.S. dollar, I will here describe our near-term demand in terms of our revenue in U.S. dollar. We now concluded our second quarter with revenue of minus 6% quarter-to-quarter and plus 3% year-to-year in U.S. dollar. As we forecasted in our previous conference, the second quarter was impacted by a quite severe inventory adjustment from fabless customers, and we saw fabless customer inventory quickly by adjusting during this period. Combining the first and the second quarters, our first half 2017 revenue will grow 12% year-to-year in U.S. dollar, higher than our guidance of 10% year-to-year growth we've estimated in our January conference. On the fabless inventory, with fabless companies' revenue going through recovery and the above-mentioned inventory management, fabless DOI has substantially decreased but still slightly above seasonal exiting Q2. We estimate the fabless inventory will continuously reduce and will come to about seasonal level at the end of third quarter. Coming to the third quarter, we forecast our third quarter revenue will grow 15.7% quarter-to-quarter. This growth is driven by a fast ramp-up of 10-nanometer mobile customer products, but moderated by the continuous inventory adjustment. We expect China smartphone market, after a slow demand period in the first half, will start to recover with new models to launch in the third quarter 2017. Other than smartphone, we continue to see good momentum in industrial and automotive sectors. So we raised this year's worldwide non-memory semiconductor growth rate from 4% to 6%. This is primarily due to a richer product mix in several markets, including computing, communication and automotive. We also increased this year's foundry growth forecast from 5% to 6%. For TSMC, we reiterate our full year 2017 growth will be in the range of 5% to 10% in U.S. dollar. Now my second key message is about 7-nanometer that include our N7 and N7+ and its outlook. TSMC's N7 has passed technology qualification in April, right on our schedule. N7 is widely adopted by our customers. We expect to have 13 new N7 product tape-outs this year. So far, N7 yield is ahead of our plan. We expect to have a very fast and smooth N7 ramp-up in 2018, with its yield learning even better than our 16-nanometer. Our N7+ technology is under development based on this robust N7 technology. We inserted several EUV layers in N7+ to take the most benefit from EUV technology with minimum risk. Our N7+ technology will be again the most advanced technology in the foundry industry in 2018 in terms of density, performance and power. This N7+ will ride on N7 learning to have a very steep yield learning curve. We also have enabled the design porting from N7 to N7+ to be very easy by carefully design rule arrangement and our strong EDA utility and IT support. We expect our 7-nanometer node, N7 and N7+, to be a major and long-life technology node. It will be used in mobile, high-performance computing and automotive markets. It will cover premium, mainstream as well as low-cost products in all those markets. Then I will briefly talk about our advanced technology progress. I would like to update our EUV progress. Both our EUV tool development and the lithography process development have progressed very well in the past six months. We have worked closely with our tool partner, ASML, who has demonstrated 250-watt EUV source power in their labs. In TSMC, EUV lithography process development also went on very smoothly. We run several EUV layers with our N7 SRAM vehicle with the same yield level as non-EUV process. Lastly, our 5-nanometer. Our 5-nanometer technology development is well on track, already with SRAM functional yield. We will offer 5-nanometer in 1Q 2019. Thank you for your attention. I turn the microphone to C.C. C. C. Wei: Thank you, Mark. Good afternoon, ladies and gentlemen. Now let me start with our 10-nanometer ramp stages. We are ramping up our 10-nanometer at full speed since last month. Currently, all the products are for mobile applications. The yield progress continue to be slightly ahead of schedule. We continue to expect 10-nanometer will contribute about 10% of our wafer revenue this year. Now let me talk about the 28-nanometer and 16 derivative. Our 28-nanometer business remains strong. In order to meet customer's demand, we have increased our 28-nanometer capacity this year, as I reported last time. In addition to the capacity increase, we further expanded and improved 28-nanometer technologies from 28HPC to 28HPC+ and now to 22-nanometer. Let me state again what I mentioned the last time about our 22 nanometers. TSMC's 22ULP offers a 15% performance gain or 35% power reduction as compared with 28HPC+. This technology is suitable for applications in IoT, ISP, GPS, WiFi, RF and 5G millimeter wave. We already have many 22ULP tape-outs ongoing and expect volume production to begin next year. With this extension of 28-nanometer, we are confident that we will continue to enjoy a high market segment share at this node. For 16-nanometer, we also extend this technology into 12-nanometer, which will have about a 10% better performance or 25% lower power consumption as compared with a 16FFC. In addition to these benefits, our 12-nanometer customers can use almost the same IP ecosystem of 16-nanometer to design better products. This resulted in much lower development costs for our customers. Now let me make a few comments on our competitive position, especially on those 16-nanometer, 28-nanometer and all the technology nodes. First of all, I want to point out that TSMC's policy is to achieve full utilization of our capacity in all nodes. We believe we can achieve this objective because we compete from a position of strength. Our strengths include; one, we develop many derivative technology to satisfy all customers' requirements; two, we are a trusted foundry by our customer; and three, our manufacturing cost is very competitive. In fact, we believe we are the lowest cost producer. We can still strive when competitors start to lose money. To summarize, we work closely with our customers to satisfy their technology and capacity requirement on both performance and cost. As a result, we are able to achieve full utilization and high market segment share. Now let me talk about the MRAM and RRAM. We have been developing emerging memories such as the MRAM, RRAM and others. The progress is to further reduce power consumption and processing cost as compared with conventional embedded flash memory, which has been widely used in applications such as MPU and PMIC. Both the MRAM and RRAM can be used in derivative specialty technologies such as the 22ULP as well as the more advanced technologies such as the 16FFC and 12FFC. In addition to wafer processing technology, we have been developing advanced packaging technologies to enhance customers' product performance. We started in 1999 with eutectic bumping, and then moved on to copper bumping, and now we have wafer-level packaging such as InFO and CoWoS that delivered more integrated values to our customers. Both the InFO and CoWoS has been in mass production, and their applications include mobile and high-speed computing. We think our advanced packaging technology are a clear differentiator for TSMC and will find many ways into artificial intelligence-related applications. We continue to work with many customers for their new products which are planned for the next 2 years. Thank you.

This concludes our prepared statements. Before we begin the Q&A session, I would like to remind everybody to limit your questions to two at a time to allow all participants an opportunity to ask questions. Questions will be taken both from the floor and from the call. Should you wish to raise your questions in Chinese, I will translate it to English before our management answers your question. [Operator Instructions] Now let's begin the Q&A session.

First, the question will be coming from Credit Suisse, Randy Abrams.

First question on some of the graphics companies have seen a lot of design win traction both in the data center and automotive space. I'm curious, based on that success from some of your customers, do you see potential for better growth from high-performance computing relative to what you outlined and potential, this could take your growth above that 5% to 10% target?

Yes, we still maintain our long-term growth. It's between 5% to 10%. This is -- indeed, there are many exciting development in the high-performance computing as well as artificial intelligence. However, this growth is really in the beginning stage and very difficult to forecast three or five years down the road. So at this point, we maintain our long-term forecast.

The second question, more on the near term. Factoring we had a lower first half from the inventory correction, and you're heading into a steep product ramp for smartphone, could you give an initial view if seasonality shifts and you expect, say, better-than-seasonal fourth quarter, first quarter, at least how it looks at this stage, maybe for Q4 and Q1, the initial view?

Randy, are you asking smartphone market?

Asking over -- for the overall company, just factoring first half was slower and you also have a steep ramp that looks a little bit later this year. If you could push seasonality out that, say, fourth quarter, first quarter might be better than in the past.

Next year, you mean?

Fourth quarter this year, first quarter next year.

Fourth quarter, yes, we just forecasted that -- this third quarter is very high quarter-to-quarter growth, and we expect fourth quarter will be -- we didn't do forecast. We expect -- it's a pretty strong quarter. Lora just estimated that year-to-year, we should be grow by 5%?

Second half to second half.

Second half to second half. So that is showing the growth momentum of the second half this year.

And just to follow up on that. The margin, you mentioned about 2 to 3 point impact on margin in the third quarter. If there's a steeper ramp into fourth quarter, do you expect similar impact, given you'll start to get scale and learning, or would the impact start to come down?

For second half, we will be affected by the 10-nanometer ramp, I was just talking about. But also, we are seeing a strong third and fourth quarter, which we believe utilization will be higher, so that's a positive. So we have negative and positive.

Then the next question will be coming from Deutsche Bank's Michael Chou.

Actually, the HPC, Mark gave the expectation before, it's $15 billion for foundry TAM in 2020, $15 billion foundry TAM for HPC in 2020. So do you have any update for that number?

You're asking me the TAM of HPC in 2020. Again, HPC, as Randy asked earlier, it's really in the initial growth period. It's very difficult to forecast the TAM in 2020, but I can see what -- today, the HPC sector, I include server, networking storage and gaming. We recently added into AR and VR, which has just started. This sector, we estimate total TAM is about $10 billion to $11 billion today -- this year. And we estimate this industry TAM growth will be about 10% a year, and we strive to grow several percent point above that.

Second question is regarding the outlook for each segment, the outlook for each segment in terms of the...

I can tell you the segments for the third quarter, which we just gave the guidance. As you can see from the guidance, we're guiding around roughly 16% Q-over-Q growth. So we expect all major segments will grow across the board. Every segment will grow, okay?

Each segment will have similar growth?

No, no, no. Computer and Consumer will grow better, but those two segments account for smaller revenue of TSMC, and the biggest is the Communication. We do expect that Communication will continue to grow.

Can we say that between wireless and wireline that the growth rate between wireless -- you don't really comment on that, but can you highlight, is there demand from wireless picking up strongly over speakers and wireline?

I will not comment sub-segments, sorry.

Next question will be coming from Citigroup's Roland Shu.

If I just look at your 3Q revenue guidance, actually, if I use the exchange rate of 30.3% that you have guided for the gross margin, and then in NT dollar terms, actually, it is smaller than if we multiply June monthly sales by three. So it means for single month revenue point of view in 3Q probably will be lower than the monthly sales in June. So for me, actually, I'm thinking now we are ramping up 10-nanometer shipment sharply, so that is the 10-nanometer, like C.C. said, is going to contribute about 10% of total revenue in this year. But in first half, we only have 1% in second quarter. So that means that we're going to have very strong 10-nanometer revenue in 3Q and 4Q. However, in 3Q, our revenue guidance is still smaller than -- I just times June monthly sales by three. So what is the weakness for the technology point of view for the revenue contribution in 3Q?

I will not recommend you look at monthly number and use that monthly number times three because it does fluctuate month-to-month, okay? For third quarter, as Mark has been mentioning, the inventory correction will continue through the third quarter, which is a little bit longer than we earlier expected. That is why the third quarter doesn't look as strong as people would expect.

But do you see any customer, they just change or defer their wafer shipment in 3Q and defer their shipment in 4Q?

No, no, we don't see that. I think what's behind it is that the OEM and channel of smartphone, actually, inventory is back to normal at the end of second quarter. And come to the third quarter, the smartphone, particularly in China, will start pulling shipment. However, our fabless customers still have a higher-than-season inventory. So it takes a little bit longer for us to ride synchronously with the end market.

Okay. From a gross margin point of view, can you remind us, if everything is equal, for every one percentage point of the utilization change, how much impact on the gross margin? I think Lora used to give us this number previously, right?

Yes, I did say it's about 0.4 percentage points. Just coincidently, same as the 1% of the foreign exchange rate. But it does fluctuate depending on which technology. But in general, I would still say about 0.4 percentage points.

Okay. And we know you put in some production in second quarter. So the actual utilization in second quarter probably will be higher, like if we just divide the shipment to the total capacity. So question is, what's the difference between the 2Q actual utilization versus 3Q actual utilization?

I probably cannot comment the utilization on second quarter and third quarter. But what you said earlier that in preparation for the 10-nanometer shipping in third quarter, which will be account for 10% of our revenue, we did start to prepare a work-in-process in second quarter. So that helped a little bit on the second quarter utilization as well.

Okay. Yes, and for the 4Q, I now expected very strong growth for 4Q, means also the utilization probably will be higher. So that is we can use the 2 to 3 percentage point dilution from 10-nanometer ramp. And then if we have higher utilization, then we can add, just I'd use this multiple, 0.4 to calculate the gross margin. Am I right?

Theoretically, okay? But we have to see what will be the actual utilization in the fourth quarter, okay?

Okay. The following questions will be coming from Daiwa's Rick Hsu.

This question is on your 10-nanometer ramp-up. Could you give us a little bit more color about your revenue contribution in Q3 and Q4? Is it possible?

C.C. just mentioning the 10-nanometer wafer revenue contribution from 10-nanometer will be 10%. And for the whole year, we expect the 10-nanometer will account for 10% of total company's whole year wafer revenue.

So can you break it down in Q3 and Q4? No?

I will not break down to Q4, okay?

Then one follow-up question is also on your 10-nanometer. What's the manufacturing cycle time for 10-nanometer as compared with the 16, like how much a percentage increase? C. C. Wei: The manufacturing cycle time you are talking about is a total cycle time?

You're right. Like how many days for total cycle time in 10-nanometer? C. C. Wei: Let me say that the cycle time, actually, we're calculating the -- how many days per layer, and it's very comparable. Actually, 10-nanometer is a little bit better than 16.

But your -- layer account for 10-nanometer should be... C. C. Wei: Much larger, much larger. The layer count is about something 20% more than 16.

All right. The following questions will be coming from UBS, Bill Lu.

Dr. Liu talked about the leadership of 7-nanometers in terms of technology and also TSMC's overall cost leadership. We're now, I guess, a little bit more than a year away from EUV. Can you talk a little bit about the cost advantages of EUV? Can you -- do we have a little more clarity on the -- on quantifying the cost advantages? I'm asking that because your competitor is doing non-EUV 8-nanometer. So I'm wondering, if we look out into the next one to two years, does your technology leadership and your cost leadership widen?

EUV is progressing rapidly, and we started the 7+ very early. And this EUV technology insertion in N7 is not only meant to do the cost reduction, the wafer cost reduction, but also to increase the density and increase the performance, transistor performance. So this technology is just -- not just the cost reduction. It has the performance and density increases. As far as the EUV, I think we can reduce the cost by adopting the EUV on 7-nanometer.

So you don't want to quantify that right now?

Right. I think our people always do better than I quantify it. So right now, it's really early to give you a number, yes.

And then the second question is for Dr. Wei. It's pretty unusual for TSMC to see this kind of revenue on 28 this far after the initial introduction. Can you tell us the outlook for 28 over the next several years in terms of volume demand? C. C. Wei: We have increased the capacity due to the strong demand, as I stated. So we have confidence that in the next few years, because we extended technology to 22, and that can be applied to a lot of other area, like ISP, like 5G millimeter wave RF. So we are confident that we get prepared, and the outlook looks good.

Maybe I'll ask that a different way. So you're increasing capacity by 15% this year. Are there plans to add more in the subsequent years? C. C. Wei: We will continue to improve the productivity. But the capacity, I cannot tell you that how much we will going to continue to increase.

If I can make some comments in addition to Mark and C.C. The capacity increase for 28-nanometer, as you mentioned, it was 15%. But out of this 15% we did increase some newly add capacity. But at the same time, we are also driving the productivity improvement. So on that 15%, there are about 5% contributed from the newly added capacity for this year, and the big portion coming from productivity improvement. Okay.

Next questions will be coming from Morgan Stanley's Charlie Chan.

So my first question is regarding your back-end service. So C.C., can you please give us some guidance about your CoWoS, 2.5D CoWoS contribution last year and this year? And going forward, do you think that a back-end service overall, InFO plus, CoWoS and bumping business can outgrow the wafer business in the coming, let's say, five years? C. C. Wei: Your first question, on the CoWoS contribution in revenue, it's still small, almost doubled from last year to this year or more than doubled, but that had been widely used in very high-performance product. So it continues to be very popular, but I think the strong growth will continue for many years. Combining the InFO and the CoWoS on the packaging technology revenue is better than the wafer revenue in CAGR. I mean, that every year, we grow much faster than that wafer revenue.

Okay. Yes, and my next question is regarding your 7-nanometer versus 10-nanometer gross margin comparison because we all know that 7-nanometer, you can use the common tools for -- with a 10-nanometer. And also, I think for 7-nanometer, you will have some more applications in HPC. I would assume that margin from the HPC customer is higher. So is that -- what's the right way to think about the 10-nanometer -- sorry, 7-nanometer margin going forward?

That's true, the 7-nanometer is this -- on the basis of 10-nanometer, so 7-nanometer has a better margin on the same peer-to-peer comparison versus 10.

Okay. Can you please quantify, for example?

Probably not.

Okay. Yes, so a quick follow-up on Bill's question regarding 28-nanometer because this year, your first half 28-nanometer quarterly revenue see a sequential decline in 1Q and 2Q. All right? So for the full year, do you expect your 28-nanometer can grow? Because you're adding capacity by 15%, right, but your revenue seems to have declined. C. C. Wei: The first half, as Mark just pointed out, is because of inventory corrections, so it's a little bit soft. Again, we increased the capacity because we see the demand coming. I can tell you that the tape-out this year is better than last year. Last year is better than the previous year. So the tape-outs are -- using the tape-outs activity, I can tell you that they still have a very bright future for 28-nanometer.

All right. I think this is about time that we will go to the line for the questions. Analysts have been queuing up on the line. So operator, please go to the first caller on the line.

Sure. The first question today comes from the line of Donald Lu from Goldman Sachs. Please ask your question.

First, I would like to just to verify a point. I think the currency assumption for gross margin for Q3 is $30. And also, Lora, can you repeat the guidance for the second half revenue?

I didn't give the guidance for second half. I was talking about the guidance for the third quarter. So your question is on the currency impact. I think I was saying nearly 100% of TSMC revenue are in U.S. dollars. So every 1% foreign exchange fluctuation will impact our gross margin by 0.4 percentage point. That's what I said. Did that answer your question?

I thought we commented on the TSMC's revenue in the second half this year on a year-over-year growth basis. There's a number. I remember at least in the last conference call, there was a 5% guidance in U.S. dollar terms.

Yes. I think the first quarter, Chairman mentioned that second half of '17 over second half of '16, we expect the U.S. dollar revenue to grow about 5%, and we still -- Mark also reiterated our view, so we're still with that opinion.

Okay, great. And in Q3, the gross margin guidance is based on 30 exchange rate between USD and TWD...

30.30, 30.3, that was the assumption, yes.

Okay. Yes, my second question is more on the 7-nanometer. I think Mark mentioned that the N7+ would be the most advanced foundry process next year. Could you give more color in terms of more specific, like the more advanced in terms of performance or cost, et cetera, compared to other foundry suppliers?

Okay. First of all, yes, we plan to offer our N7+ in the middle of next year, 2018. And that technology is with EUV volume production. The reason I mentioned N7+ in such emphasis is our customer who are using our N7 today can migrate to N7+ very easily. Therefore, the current -- we established our N7+ customer base on this N7 customer. We have already more than 30 customers on N7 today. Secondly, the yield learning, by then, we should have volume production on N7. And N7+ is just ride on the same yield learning curve. We won't start from a brand-new technology. And that's including the fact I mentioned earlier, this N7+ have, I think, we, in technology symposium, we mentioned about the density and performance improvement, definitely put this technology in the forefront of any foundry technology at the time.

Right. But if your customer and your competitors use EUV on more layers than TSMC, would that potentially make their products less expensive?

Well, at this point, I don't want to answer hypothetical questions, okay? And we'll see. I think we'll be posed very competitive and we'll be very, very agile in responding to competition all the time.

Well let's move on to the next caller on the line, operator please.

Our next caller on the line, comes from Mehdi Hosseini from SIG. Please ask your question.

Just a follow-up on EUV. You said that 7, you will offer EUV in the second half of 2018 on 7-nanometer plus. And then full insertion in Q1 of 2019. It will be great if you could help us with the level of insertion. I imagine when you talk about 7-nanometer plus, the insertion is for a couple of critical layers. And then with the full insertion, it would increase to maybe 10 to 12 critical layers, and I was wondering if you could elaborate on it, and I have a follow-up.

So Mehdi's question is how many layers do we intend to input on our 7+, and how many layers we will use on EUV for N5.

I really don't want to tell you how many layers we inserted in N7+ at this time, because everybody is hearing that and is positioning. So allow me to tell you that there will be cost reduction, that will be very easy to adopt, you don't start from a new technology, and there will be minimal risk for our customer to ramp.

Sure. Because -- okay, let me rephrase my question. I think Lora mentioned that the margin profile for 7 is going to be better than 10-nanometer, and EUV will cost more. So does that mean that the non-EUV layer would benefit from some equipment reuse? C. C. Wei: Well, on the EUV, I think there is more than 90% of 7-nanometers equipment from 10-nanometer. Does that answer your question?

Yes, yes, yes. I have one quick follow-up question on the 16-nanometer. How should we think about the 16-nanometer revenues in the second half of '17 versus second half of '16? C. C. Wei: Lora, can you take that?

I think our 16-nanometer revenue for this year should be higher than last year.

So you should see a rebound in the second half, correct? Because it has been declining Q-o-Q in the first half.

Sorry, I was referring to year-over-year. You're actually asking for second half versus first half. Is that your question?

Yes, yes, yes. Because I'm just trying -- yes, in the first half, it has been declining -- your customers -- your smartphone customers are going to migrate to 10-nanometer. And I'm just trying to better understand how you're going to be able to refill 16-nanometer?

We have 12-nanometer, as you may know. And 16-nanometer has the same equipment for 12-nanometer. So as we start to ramp 12-nanometer later this year through to 2018, 12-nanometer can very well backfill our 16-nanometer capacity next year.

Our next question today comes from the line of Patrick Liao from Macquarie. Please ask your question.

Yes. Does TSMC focus on back-end, that is InFO process, that we can anticipate some clients with demand for their needs except for Apple?

Patrick, please repeat your question again?

Hello, can you hear me?

Yes, we can hear you, but please repeat your question.

Yes. Does TSMC focus on back-end, that is InFO process, that we can anticipate some clients with demand for their needs except for Apple? C. C. Wei: Well, I cannot comment on this one for a specific customer.

So Patrick, you are asking if we have other customers on InFO other than Apple. Is that your question?

Yes, yes, that's my question. C. C. Wei: We are working with many customers, but -- so again, but the high volume production for other customers, for a lot of our customers, will begin next year.

Okay. I have a minor question. Is 28-nanometer a breakthrough node that clients seem to have chosen high-K metal gate or Poly/SiON gate mostly?

So you are saying 28-nanometer has Poly/SiON and high-K metal gate, and then what about them?

Yes, which -- these two gates, which one would be chosen mostly from TSMC's experience right now? C. C. Wei: Well, the high-K metal gate version probably is the one we extended into the next node, 22-nanometer. Is that answer your question?

A little bit, because that some of your competitors is right now, their major focus on Poly/SiON gate. So I want to get an idea about high-K metal gate, how about the usage in your -- in TSMC's experience?

So which one do we focus more? Are we focusing more on high-K metal gate or we are focusing more on Poly/SiON?

Yes. C. C. Wei: We are -- okay, we continue to improve the technology from 28-nanometer to 22. I can tell you that 22 is all on high-K metal gate. Does that answer the question?

Okay, okay, that answers my question.

Thank you and now let's come back to the floor. The question will be coming from JPMorgan's Gokul.

First question on 7-nanometer. Just wanted to get the numbers right. I think last time, Dr. Liu, you mentioned 15 tape-outs. Right now, I think it's 30, 3-0, in terms of 7-nanometer tape-outs that you're seeing. Could you talk about what proportion of that is HPC? Because last time you mentioned almost half of those are HPC-related products.

It's right now, you mean, among the tape-outs?

Yes, among the 30 tape-outs that you have.

Still more than half.

More than half are HPC. And when you think about 7 and 7+, do you feel that when you talk to and engage with the customers, are more -- most customers basically looking at it as very easy migration or is it like there are customers who wait for 7+ or some customers who basically stay on 7 for a longer period of time? Do you expect like most of the customers eventually go to 7+ from 7?

Yes. Most of the customers, after we work with them, actually, they sent us the tape. We ported for them for certain function blocks and proved to them it's very easy and each customer, we plan to do that and we've done several already.

Okay. Just one other question on customer concentration. I think the customer concentration has been rising, I think, in the last three, four years. I think it looks like this year also it will move up, given your biggest customer has a very strong product cycle. How should we think about customer concentration when we get to 7-nanometer and 7-nanometer plus? Given that the number of tape-outs seems to be much higher, do you anticipate the customer concentration to fall or is it still going to be relatively high? And maybe also try to be even maybe what is the importance of system customers within this, especially the larger leading-edge kind of process nodes? Are system customers becoming a bigger and bigger part of the customer base, especially for leading-edge?

Our top 10 customers account for 64% in 2015. And that number went up to 69%, as you can see from our annual report. This is mainly because there are consolidations among customer base. For this year, we expect the concentration will come down a little bit. But I want to say that people may feel customer concentration is not a good thing. But we feel the other way. It's not really a bad thing, because when you have a bigger customer, that means the dependency for them to TSMC as the customer and for us to then as the supplier needs to be stronger, the relationship collaboration needs to be stronger, which is in favor of a foundry business model. So we view that as a positive thing.

Could you also talk about system customers? How important are system customers becoming as we go from, let's say, 20/16 to 7-nanometer, given the number of tape-outs that you've got?

Well, there are different system company, system customers. Some customers design on their own. Some customers ask our customer to design for them. And some customers ask our support to design, mostly using through third-party design service companies. So there are different forms of the system company getting into this own design in semiconductor. We welcome that, too, because that will speed up the innovation of the chip, connecting the chip design directly with the system application. And I think that our customer also share a part of those business to grow. And indeed, that's a big portion of the future growth.

All right. Next question will be coming from Credit Suisse, it's Randy's follow-up.

The first question, wanted to clarify on the 7+ and the 5. Last quarter, I think you talked about those stages at risk production and then the volume one year later. Has the schedule changed and it's now you expect the revenue ramp-up in that earlier time, or is there still about one year from availability to the volume ramp-up?

Yes, we estimate it's still about a year, not really the technology on our side. It's really on their design, product qualification and system verification get to the market. It typically takes that long. Although for the mobile, it's about one year. Some of the high-performance computing or PC application will be shorter. So -- but that 7 and 7+, I don't see much difference in the lead time up to the volume.

Okay, a follow-up to that. Are you seeing most customers waiting then for 7+ with EUV, given the enhancements and staying, say, with 12-nanometer? Or do you see actually still the same fast migration from 10 to 7 next year?

Because 7 and 7+, they share same design ecosystem and the porting, so no, I don't see that.

Just one quick follow-up. Do you see potential we could actually have a bit of a lower CapEx budget, just given the 90% reuse? Or in top of the 90%, because of the layers, there should be still pretty meaningful or similar spend next year?

The EUV itself will not necessarily reduce the CapEx per 1,000 wafer investment because the complexity of 5-nanometer especially. However, as we are continuing to drive the productivity, so the CapEx per 1,000 wafer go down because of that reason. So if the two things offset each other, it's not necessary the EUV adoption will affect the CapEx per K too much.

Okay, just to clarify, I was talking next year where you're migrating from 10- to 7-nanometer, if you expect that tool reuse, given the common tools, that could allow, say, a lower year for CapEx, from 10 to 7, given the tool reuse?

In addition to the transition from 10 to 7, we also will increase the total capacity next year. So that will compose the total CapEx.

Okay. There are still quite a few callers on the line, so let's move back to the line. Operator, please have the next caller.

Our next question on the line comes from Brett Simpson from Arete Research. Please ask your question.

I just wanted to get your perspective on a couple of trends in smartphones that seem quite fundamental to your business. First of all, a lot of chipmakers are saying that we're going to start to see AI being processed on the phone. So we're going to see new classes of accelerators dedicated for AI in the smartphone. Can you maybe just talk about this in more detail? And is this something you see being produced at like 16-nanometer? Is it part of the reason why you're adding 28-nanometer capacity or is it going to be 7-nanometer? So that's the first question. And the second one is ARM. ARM are talking about material challenges with thermals in smartphone chips and application processors. A lot of dark silicon issues, which is leading to bigger die sizes or certainly new architectures. Can you maybe just give us your perspective on leading edge die sizes for smartphones? Are we going to see a rise in silicon content as a result in smartphones?

So Brett's question, first part is with respect to artificial intelligence used on phone, and he's asking what is our perspective on the direction of having new accelerators used in AI to be put on the phone, and are they going to use 16-nanometer or 28-nanometer type of process? And the second part is ARM commenting on material challenges, particularly with respect to thermal issues on chips. And he's asking if we are -- we can comment on solutions like new architectures and other aspects to solve this problem.

Well, I think many of those information is really our customers' confidential. So I won't -- I wouldn't want to -- I cannot talk about it. But AI is indeed getting to smartphone. That's for sure. And that is -- actually, AI is going to every segments in our growth sectors. AI is getting to mobile. AI is getting to high-performance computing like deep learning. AI will go into automotive, which is ADAS and so forth. And AI will go to simple IoT, MCU also. So this AI is a general application driver of momentum -- put this way, one of the driver -- driving momentum, and it is ubiquitous. And I wouldn't comment on the -- I think our customers will adopt AI whenever possible and doesn't limit it to a certain technology.

Brett, do you have a follow-up question or this is good enough?

Well, I mean, just one follow-up. I understand that AI is a ubiquitous trend. But specifically, Google has talked about their next oval leaves, there's going to be accelerators coming out later this year. I think we hear about Apple Neural Engine. There's a significant shift happening which would suggest smartphone content is going to rise for -- semiconductor content is going to rise in smartphones because of AI. And I don't know whether you see this accelerating the smartphone growth rates that you see over the next couple of years.

Yes, I think it will, just for the reason you just stated.

Our next question today comes from the line of Peter Chan from CIMB. Please ask you question.

I have a question regarding the storage class memory. C.C. mentioned about the MRAM, RRAM earlier. Just wondering is this TSMC's answer to Intel's 3D XPoint? And how would this two help the customer to develop future applications? And is there any difference between the MRAM and the RRAM? For example, is RRAM more suitable for, say for example, automotive; MRAM is more suitable for consumer. What would be the strategy of the -- in terms of application for those two? C. C. Wei: When we developed emerging memories, we cooperate with the customer and due to their requirement, not specifically we are going to talk about the XPoint memory that's proposed by another company, so -- and the applications, they actually -- yes, you are right, it's mostly in automotive and also in MPU, in a lot of area. Which one that customer like to adopt, that depends on their product requirements, because different product has a different kind of retention time, different kind of endurance requirement. So sometimes, they use RRAM, sometimes they use MRAM, and I will not comment on that.

Okay. As a follow-up to that, for MRAM, RRAM, assuming that this will be offered to customer as embedded solution, and are this going to be -- do you consider these are the essential elements to address the future applications in AI?

So the question is since MRAM, RRAM are embedded solutions, are they critical to address future needs of AI? C. C. Wei: Probably the answer is that they are very critical to every area, that whenever you need embedded memory inside, to replace or not, just to get the lower cost and lower power consumption for IoT, for automotive and Mark just mentioned that AI is everywhere. So to answer your question, yes, and in a lot of applications.

Okay, let's come back to the floor. The next question will be coming from HSBC's Steven Pelayo.

Just a couple of quick follow-ups. First on Mehdi's question, with a little 16-nanometer focus, but I guess combination 20 and 16 is about 25%, 26% of revenues. It looks like it's down the last few quarters versus 28-nanometer being relatively steady for the last four to six quarters or so. So could you quantify a little bit looking into the third quarter and the fourth quarter, do you expect growth in that 25% of revenues of that 20 and 16-nanometer node?

No. We think the 20 plus 16 revenue in the following two quarters will come down somewhat. It will not be as high as second quarter.

Okay, fair enough. And then on, another 25% of revenues is in your Industrial/Standard. I'm wondering if you could just help us think a little bit more about that? How much is industrial, how much is auto, how much is -- how do you break down that quarter of the company?

I would like to mention three big subsegments on that Industrial/Standard. I think the top three are MCU, power INCREASE and data converter. They account for the majority part of the Industrial/Standard.

Okay. And then just quickly, depreciation was down a little bit quarter-on-quarter, but also you've got a ramp of a lot of expensive capacity coming. Could you talk a little bit about third quarter depreciation? Will it grow faster than your revenue guidance, and outlook for depreciation for the full year?

The depreciation for the whole year with the 10, about TWD 10 billion CapEx will be high teens, let's say, 17% to 18%, okay? So you can expect second half depreciation will come up faster growth than the earlier quarter.

Okay. Then maybe the last question for Mark or C.C. We're seeing the first 10-nanometer chips being tore down that you're producing, and massive die size shrinks, on an apples-to -- or maybe I should say like-for-like basis instead of saying apples, upwards of 40%, 50% type shrink. So I'm curious, what does that mean from a capacity planning perspective for you? Do you need to build as much physical wafer capacity, because your customers are taking advantage of much more stronger shrinks at 10-nanometer? C. C. Wei: I don't comment on customers' die size per se, whether it is going to reduce the requirement on the wafer, we ramp up quickly, and with, again, 10% wafer revenue for the whole year. So you can calculate it.

Okay. The next questions will be coming from Citigroup's Roland, Roland Shu.

Yes, we know AI is for everything. How about -- I think we would like to know how about the AI at TSMC? Because in your annual report, you said that you've already built a team to dedicate doing this machine learning and AI development. So can you share with us what's your progress for this machine learning and AI development? And what can we expect once you implement your AI in your production line? What kind of change it will be? C. C. Wei: Well, we utilize the AI technology in our own manufacturing area most, so we use that one to improve the defect density, to improve the productivity and also, at the same time, to improve the quality. And how we did it, it's company confidential.

So you've already implemented on your production line? C. C. Wei: Yes, we did.

Okay. So when you talk about that you have this efficiency improvement, actually the part of it had been achieved by this AI adoption? C. C. Wei: Yes.

Okay. Second question for C.C. Last year, you spent 1 billion CapEx in InFO and you ramped up InFO revenue to $500 million this year. And this year again, you are going to spend 1 billion CapEx in back-end. So can we expect next year, we can generate another 500 million revenue on InFO and that will go back -- go up to 1 billion in total revenue next year? C. C. Wei: We put the CapEx for the back-end area, not 100% for InFO. Okay, we still have a CoWoS. We still have a lot of testing. So I cannot comment, say that next year what the revenue would be. But this year, 500 million.

So are we spending a similar amount of the CapEx in InFO this year? C. C. Wei: I won't comment on that.

Next question will be coming from Morgan Stanley's Charlie Chan.

So for second quarter, your Industrial segment outgrowing other segments. So can you elaborate a little bit what kind of semiconductors or applications in that Industrial and others segments?

Well, second quarter, Industrial/Standard mostly come from MCU, power and data converter, in particular application in automotive and factory automation, those applications.

Okay, understood. And same question is regarding your business strategy in trailing edge. I guess this question is to C.C. So you mentioned that you want to fully utilize your fab space. So I'm asking whether you would reduce your price regardless to get your fab to 100% utilization? Because no one can compete with your cost structure. And I guess most of your trailing edge tools already fully depreciated. So what is right way to maximize your company's profits and shareholders' return? C. C. Wei: Technology. Technology, the weapon that we are using most. So we've developed a lot of derivative technology to meet customers' requirement. That reduced their die cost, at the same time, improved the performance. And that is where we get the business.

So can I assume that you will fulfill your trailing edge capacity to 100% regardless whatever... C. C. Wei: That's our goal. That's our goal.

That's your goal? C. C. Wei: Yes.

Next question will be coming from Deutsche Bank's Michael Chou.

Lora, what is the total capacity increase magnitude this year?

If I remember correctly, it's about 10% year-over-year.

Okay. Second question is management seemed to mentioned that last year, 20% reduction in cycle time. So would you reduce the cycle time further this year to improve the cost structure? C. C. Wei: I cannot give you the specific number because that is confidential, but we'll continue to improve, that I can say.

So as a follow-up question, sir. Do you think when you enter 7-nanometer, you will continue to reduce cycle time further? Because you mentioned 10-nanometer per layer, cycle time seems to be lower... C. C. Wei: Reduced.

Yes, yes. Do you think that, that will continue to 7-nanometer? C. C. Wei: We definitely do, it's our goal. Yes, we have other weapons.

Next question will be coming from CL's Sebastian Hou.

My first question is for Mark, that do you have any committed customers or any tape-outs confirmed on N7+ right now? And what type application is that? Is it for mobile or for HPC?

That will happen in the 2018.

So it's not -- so no one is confirmed right now.

Well, they are customer who are committed to use it, but they don't have a specific tape-out date for that. Most of them are working on N7 today.

So for those customers who are in -- who show their initial commitment to use it, are they coming from both mobile and HPC?

I think both, just like N7, particularly those leading users, yes.

Second question is on your high-performance computing in terms of the margin and profit impact to TSMC as a whole, that theoretically, we would think that it is for data center or for server, so it's higher-margin or difficulty to do than customer-type other products, from that perspective. But at the same time, it's also harder to make, die size larger, so process control become more important. So what's the net-net impact in terms of the margin profitability for TSMC, from operating margin perspective?

At this point, the net-net impact -- net-net impact is no impact to our gross margin as we estimate today.

Next question online comes from Douglas Smith from Agency Partners. Please ask your question.

Just to clarify on the N7+, am I correct in assuming that you're going to target 250-watt source and mask with fully working pellicle? And do you see any potential bottlenecks in terms of either the masks or the resists for EUV for N7+?

The 250-watt still happen in the laboratory, and we don't count on that high number to do the cost reduction. Currently, we estimate if we do well on 125, for example, it will be sufficient enough for us to make the cost reduction.

And in terms of pellicle, do you think that's necessary or it's not necessary for N7+?

We have very active pellicle development today and we will prepare for both. If we have to use it, we have no problem by then.

Our next question today comes from the line of Mehdi Hosseini from SIG. Please ask your question.

Just a couple of follow-ups. Lora, can you please tell me how should we think about depreciation this year? Did you say it would be up 17% to 18%?

Yes. This year's depreciation will be 17% higher than last year.

And then, how should we think about the capacity that is going to move to China? When is the timing and how would it impact the depreciation schedule as that capacity is in transit? C. C. Wei: We start to move the equipment in the second half of this year, and then we expect the production in second half of next year. As far as the depreciation, I don't think there's any impact at all.

Okay. And is it -- I think in the past, you've talked about like 20,000 to 30,000 wafer per month and it's going to be mostly 12-nanometer, 16-nanometer. Is it still the case? C. C. Wei: We talked about 20,000 wafer per month and 16 nanometers technology. That's what we said. It continues to be the same situation.

Thank you, Mehdi. And I think we have exhausted all the questions from our audience, and we are happy to draw a conclusion of our conference call now. Thank you, everybody, for attending. And we'll look forward to see you next quarter.